UNIT 1: Introduction to Electronics Number Systems and Conversion

1.1 Digital Systems and Switching Circuits

1.2 Number Systems and Conversion

1.3 Binary Arithmetic

1.4 Representation of Negative Numbers

1.5 Binary Codes

UNIT 2: Boolean Algebra

2.1 Introduction

2.2 Basic Operations

2.3 Boolean Expressions and Truth Tables

2.4 Basic Theorems

2.5 Commutative, Associative, Distributive, and DeMorgan’s Laws

2.6 Simplification Theorems

2.7 Multiplying Out and Factoring

2.8 Complementing Boolean Expressions

UNIT 3: Boolean Algebra (Contd)

3.1 Multiplying Out and Factoring Expressions

3.2 Exclusive-OR and Equivalence Operations

3.3 The Consensus Theorem

3.4 Algebraic Simplification of Switching Expressions

3.5 Proving Validity of an Equation

UNIT 4: Applications of Boolean Algebra Minterm and Maxterm

Expansions

4.1 Conversion of English Sentences to Boolean Equations

4.2 Canonical Form

4.3 Generation of Switching Equation from Truth Table

4.4 General Minterm and Maxterm Expansions

4.5 Incompletely Specified Functions

4.6 Examples of Truth Table Construction

UNIT 5: Karnaugh Maps

5.1 Minimum Forms of Switching Functions

5.2 Two- and Three-Variable Karnaugh Maps

5.3 Four-Variable Karnaugh Maps

5.4 Determination of Minimum Expressions Using Essential Prime Implicants

5.5 Five-Variable Karnaugh Maps

5.6 Other Uses of Karnaugh Maps

UNIT 6: Quine-McCluskey Method

6.1 Determination of Prime Implicants

6.2 The Prime Implicant Chart

6.3 Petrick’s Method

6.4 Simplification of Incompletely Specified Functions

6.5 Simplification Using Map-Entered Variables

UNIT 7: Multi-Level Gate Circuits NAND and NOR Gates

7.1 Multi-Level Gate Circuits

7.2 NAND and NOR Gates

7.3 Design of Two-Level NAND- and NOR-Gate Circuits

7.4 Design of Multi-Level NAND- and NOR-Gate Circuits

7.5 Circuit Conversion Using Alternative Gate Symbols

7.6 Design of Two-Level, Multiple-Output Circuits

7.7 Multiple-Output NAND- and NOR-Gate Circuits

UNIT 8: Combinational Circuit Design and Simulation Using Gates

8.1 Review of Combinational Circuit Design

8.2 Design of Circuits with Limited Gate Fan-In

8.3 Gate Delays and Timing Diagrams

8.4 Hazards in Combinational Logic

8.5 Simulation and Testing of Logic Circuits

UNIT 9: Multiplexers, Decoders, and Programmable Logic Devices

9.1 Introduction

9.2 Multiplexers

9.3 Three-State Buffers

9.4 Decoders and Encoders

9.5 Read-Only Memories

9.6 Programmable Logic Devices

9.7 Complex Programmable Logic Devices

9.8 Field-Programmable Gate Arrays

9.9 Design of Binary Adders and Subtracters

9.10 Binary comparator

UNIT 10: Introduction to VHDL

10.1 VHDL Description of Combinational Circuits

10.2 VHDL Models for Multiplexers

10.3 VHDL Modules

10.4 Signals and Constants

10.5 Arrays

10.6 VHDL Operators

10.7 Packages and Libraries

10.8 IEEE Standard Logic

10.9 Compilation and Simulation of VHDL Code

UNIT 11: Latches and Flip-Flops

11.1 Introduction

11.2 Set-Reset Latch

11.3 Gated Latches

11.4 Edge-Triggered D Flip-Flop

11.5 S-R Flip-Flop

11.6 J-K Flip-Flop

11.7 T Flip-Flop

11.8 Flip-Flops with Additional Inputs

11.9 Asynchronous Sequential Circuits

11.10 Summary

UNIT 12: Registers and Counters

12.1 Registers and Register Transfers

12.2 Shift Registers

12.3 Binary Ripple Counter

12.4 Design of Synchronous Binary Counters

12.5 Counters for Other Sequences

12.6 Synchronous Counter Design Using S-R and J-K flipflop

12.7 Derivation of Flip-Flop Input Equations -Summary

UNIT 13: Analysis of Clocked Sequential Circuits

13.1 A Sequential Parity Checker

13.2 Analysis by Signal Tracing and Timing Charts

13.3 Construction of State Diagrams

13.4 Mealy and Moore Models

13.5 State Machine Notation

13.6 General Models for Sequential Circuits

UNIT 14: Derivation of State Graphs and Tables

14.1 Design of a Sequence Detector

14.2 More Complex Design Problems

14.3 Guidelines for Construction of State Graphs

14.4 Serial Data Code Conversion

UNIT 15: Derivation of State Graphs and Tables

15.1 Elimination of Redundant States

15.2 Equivalent States

15.3 Determination of State Equivalence Using an Implication Table

15.4 Equivalent Sequential Circuits

15.5 Reducing Incompletely Specified State Tables

15.6 Derivation of Flip-Flop Input Equations

15.7 Equivalent State Assignments

15.8 Guidelines for State Assignment

15.9 Using a One-Hot State Assignment

UNIT 16: Sequential Circuit Design

16.1 Summary of Design Procedure for Sequential Circuits

16.2 Design Example—Code Converter

16.3 Design of Iterative Circuits

16.4 Design of Sequential Circuits Using ROMs and PLAs

16.5 Sequential Circuit Design Using CPLDs

16.6 Sequential Circuit Design Using FPGAs

UNIT 17: VHDL for Sequential Logic

17.1 Modeling Flip-Flops Using VHDL Processes

17.2 Modeling Registers and Counters Using VHDL Processes

17.3 Modeling Combinational Logic Using VHDL Processes

17.4 Modeling a Sequential Machine

17.5 Synthesis of VHDL Code

17.6 More About Processes and Sequential Statements

UNIT 18: Circuits for Arithmetic Operations

18.1 Serial Adder with Accumulator

18.2 Design of a Binary Multiplier

18.3 Design of a Binary Divider

This textbook on fundamentals of logic design is targeted towards beginners who aspire to learn the fundamental concepts of digital electronics. This book covers the syllabus of major universities with systematic presentation. The concepts are explained in simple and lucid manner. Some real-time applications of the concepts are discussed. Numerous examples based on the concepts make the reader understand the subject clearly.

This book comprises of 18 chapters, each unit consisting of objectives that state precisely what the student is expected to learn by studying the unit. This is followed by concepts, solved problems, review questions, and also real-time applications to make the concepts clear---the students learn, both, theory and its application.