Fundamentals of Logic Design (Record no. 2430)
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| 000 -LEADER | |
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| fixed length control field | 06682nam a22001817a 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20240930115608.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 240930b |||||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9789353502645 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.395 |
| Item number | ROT |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Roth Charles H. |
| 245 ## - TITLE STATEMENT | |
| Title | Fundamentals of Logic Design |
| Statement of responsibility, etc. | Charles H. Roth, Jr. | Larry L. Kinney | Raghunandan G. H. |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1 |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | INDIA |
| Name of publisher, distributor, etc. | CENGAGE |
| Date of publication, distribution, etc. | 2020 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Page number | 616 |
| 505 ## - FORMATTED CONTENTS NOTE | |
| Title | UNIT 1: Introduction to Electronics Number Systems and Conversion<br/><br/>1.1 Digital Systems and Switching Circuits<br/><br/>1.2 Number Systems and Conversion<br/><br/>1.3 Binary Arithmetic<br/><br/>1.4 Representation of Negative Numbers<br/><br/>1.5 Binary Codes<br/><br/>UNIT 2: Boolean Algebra<br/><br/>2.1 Introduction<br/><br/>2.2 Basic Operations<br/><br/>2.3 Boolean Expressions and Truth Tables<br/><br/>2.4 Basic Theorems<br/><br/>2.5 Commutative, Associative, Distributive, and DeMorgan’s Laws<br/><br/>2.6 Simplification Theorems<br/><br/>2.7 Multiplying Out and Factoring<br/><br/>2.8 Complementing Boolean Expressions<br/><br/>UNIT 3: Boolean Algebra (Contd)<br/><br/>3.1 Multiplying Out and Factoring Expressions<br/><br/>3.2 Exclusive-OR and Equivalence Operations<br/><br/>3.3 The Consensus Theorem<br/><br/>3.4 Algebraic Simplification of Switching Expressions<br/><br/>3.5 Proving Validity of an Equation<br/><br/>UNIT 4: Applications of Boolean Algebra Minterm and Maxterm<br/><br/>Expansions<br/><br/>4.1 Conversion of English Sentences to Boolean Equations<br/><br/>4.2 Canonical Form<br/><br/>4.3 Generation of Switching Equation from Truth Table<br/><br/>4.4 General Minterm and Maxterm Expansions<br/><br/>4.5 Incompletely Specified Functions<br/><br/>4.6 Examples of Truth Table Construction<br/><br/>UNIT 5: Karnaugh Maps<br/><br/>5.1 Minimum Forms of Switching Functions<br/><br/>5.2 Two- and Three-Variable Karnaugh Maps<br/><br/>5.3 Four-Variable Karnaugh Maps<br/><br/>5.4 Determination of Minimum Expressions Using Essential Prime Implicants<br/><br/>5.5 Five-Variable Karnaugh Maps<br/><br/>5.6 Other Uses of Karnaugh Maps<br/><br/>UNIT 6: Quine-McCluskey Method<br/><br/>6.1 Determination of Prime Implicants<br/><br/>6.2 The Prime Implicant Chart<br/><br/>6.3 Petrick’s Method<br/><br/>6.4 Simplification of Incompletely Specified Functions<br/><br/>6.5 Simplification Using Map-Entered Variables<br/><br/>UNIT 7: Multi-Level Gate Circuits NAND and NOR Gates<br/><br/>7.1 Multi-Level Gate Circuits<br/><br/>7.2 NAND and NOR Gates<br/><br/>7.3 Design of Two-Level NAND- and NOR-Gate Circuits<br/><br/>7.4 Design of Multi-Level NAND- and NOR-Gate Circuits<br/><br/>7.5 Circuit Conversion Using Alternative Gate Symbols<br/><br/>7.6 Design of Two-Level, Multiple-Output Circuits<br/><br/>7.7 Multiple-Output NAND- and NOR-Gate Circuits<br/><br/>UNIT 8: Combinational Circuit Design and Simulation Using Gates<br/><br/>8.1 Review of Combinational Circuit Design<br/><br/>8.2 Design of Circuits with Limited Gate Fan-In<br/><br/>8.3 Gate Delays and Timing Diagrams<br/><br/>8.4 Hazards in Combinational Logic<br/><br/>8.5 Simulation and Testing of Logic Circuits<br/><br/>UNIT 9: Multiplexers, Decoders, and Programmable Logic Devices<br/><br/>9.1 Introduction<br/><br/>9.2 Multiplexers<br/><br/>9.3 Three-State Buffers<br/><br/>9.4 Decoders and Encoders<br/><br/>9.5 Read-Only Memories<br/><br/>9.6 Programmable Logic Devices<br/><br/>9.7 Complex Programmable Logic Devices<br/><br/>9.8 Field-Programmable Gate Arrays<br/><br/>9.9 Design of Binary Adders and Subtracters<br/><br/>9.10 Binary comparator<br/><br/>UNIT 10: Introduction to VHDL<br/><br/>10.1 VHDL Description of Combinational Circuits<br/><br/>10.2 VHDL Models for Multiplexers<br/><br/>10.3 VHDL Modules<br/><br/>10.4 Signals and Constants<br/><br/>10.5 Arrays<br/><br/>10.6 VHDL Operators<br/><br/>10.7 Packages and Libraries<br/><br/>10.8 IEEE Standard Logic<br/><br/>10.9 Compilation and Simulation of VHDL Code<br/><br/>UNIT 11: Latches and Flip-Flops<br/><br/>11.1 Introduction<br/><br/>11.2 Set-Reset Latch<br/><br/>11.3 Gated Latches<br/><br/>11.4 Edge-Triggered D Flip-Flop<br/><br/>11.5 S-R Flip-Flop<br/><br/>11.6 J-K Flip-Flop<br/><br/>11.7 T Flip-Flop<br/><br/>11.8 Flip-Flops with Additional Inputs<br/><br/>11.9 Asynchronous Sequential Circuits<br/><br/>11.10 Summary<br/><br/>UNIT 12: Registers and Counters<br/><br/>12.1 Registers and Register Transfers<br/><br/>12.2 Shift Registers<br/><br/>12.3 Binary Ripple Counter<br/><br/>12.4 Design of Synchronous Binary Counters<br/><br/>12.5 Counters for Other Sequences<br/><br/>12.6 Synchronous Counter Design Using S-R and J-K flipflop<br/><br/>12.7 Derivation of Flip-Flop Input Equations -Summary<br/><br/>UNIT 13: Analysis of Clocked Sequential Circuits<br/><br/>13.1 A Sequential Parity Checker<br/><br/>13.2 Analysis by Signal Tracing and Timing Charts<br/><br/>13.3 Construction of State Diagrams<br/><br/>13.4 Mealy and Moore Models<br/><br/>13.5 State Machine Notation<br/><br/>13.6 General Models for Sequential Circuits<br/><br/>UNIT 14: Derivation of State Graphs and Tables<br/><br/>14.1 Design of a Sequence Detector<br/><br/>14.2 More Complex Design Problems<br/><br/>14.3 Guidelines for Construction of State Graphs<br/><br/>14.4 Serial Data Code Conversion<br/><br/>UNIT 15: Derivation of State Graphs and Tables<br/><br/>15.1 Elimination of Redundant States<br/><br/>15.2 Equivalent States<br/><br/>15.3 Determination of State Equivalence Using an Implication Table<br/><br/>15.4 Equivalent Sequential Circuits<br/><br/>15.5 Reducing Incompletely Specified State Tables<br/><br/>15.6 Derivation of Flip-Flop Input Equations<br/><br/>15.7 Equivalent State Assignments<br/><br/>15.8 Guidelines for State Assignment<br/><br/>15.9 Using a One-Hot State Assignment<br/><br/>UNIT 16: Sequential Circuit Design<br/><br/>16.1 Summary of Design Procedure for Sequential Circuits<br/><br/>16.2 Design Example—Code Converter<br/><br/>16.3 Design of Iterative Circuits<br/><br/>16.4 Design of Sequential Circuits Using ROMs and PLAs<br/><br/>16.5 Sequential Circuit Design Using CPLDs<br/><br/>16.6 Sequential Circuit Design Using FPGAs<br/><br/>UNIT 17: VHDL for Sequential Logic<br/><br/>17.1 Modeling Flip-Flops Using VHDL Processes<br/><br/>17.2 Modeling Registers and Counters Using VHDL Processes<br/><br/>17.3 Modeling Combinational Logic Using VHDL Processes<br/><br/>17.4 Modeling a Sequential Machine<br/><br/>17.5 Synthesis of VHDL Code<br/><br/>17.6 More About Processes and Sequential Statements<br/><br/>UNIT 18: Circuits for Arithmetic Operations<br/><br/>18.1 Serial Adder with Accumulator<br/><br/>18.2 Design of a Binary Multiplier<br/><br/>18.3 Design of a Binary Divider |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | This textbook on fundamentals of logic design is targeted towards beginners who aspire to learn the fundamental concepts of digital electronics. This book covers the syllabus of major universities with systematic presentation. The concepts are explained in simple and lucid manner. Some real-time applications of the concepts are discussed. Numerous examples based on the concepts make the reader understand the subject clearly.<br/><br/>This book comprises of 18 chapters, each unit consisting of objectives that state precisely what the student is expected to learn by studying the unit. This is followed by concepts, solved problems, review questions, and also real-time applications to make the concepts clear---the students learn, both, theory and its application. |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Koha item type | Books |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) | |
| -- | 8000 |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) | |
| -- | 8001 |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) | |
| -- | 8002 |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) | |
| -- | 8003 |
| 952 ## - LOCATION AND ITEM INFORMATION (KOHA) | |
| -- | 8004 |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Collection code | Home library | Current library | Shelving location | Date acquired | Source of acquisition | Cost, normal purchase price | Inventory number | Total Checkouts | Full call number | Barcode | Date last seen | Cost, replacement price | Price effective from | Currency | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | Non-fiction | IIITDM Kurnool | IIITDM Kurnool | ELECTRONICS COMMUNICATION ENGINEERING | 30.09.2024 | New India Book Agency | 695.00 | 5395 dt 31-8-2024 | 621.395 ROT | 0006982 | 30.09.2024 | 695.00 | 30.09.2024 | INR | Books | |||||
| Dewey Decimal Classification | Non-fiction | IIITDM Kurnool | IIITDM Kurnool | ELECTRONICS COMMUNICATION ENGINEERING | 30.09.2024 | New India Book Agency | 695.00 | 5395 dt 31-8-2024 | 621.395 ROT | 0006983 | 30.09.2024 | 695.00 | 30.09.2024 | INR | Books | |||||
| Dewey Decimal Classification | Non-fiction | IIITDM Kurnool | IIITDM Kurnool | ELECTRONICS COMMUNICATION ENGINEERING | 30.09.2024 | New India Book Agency | 695.00 | 5395 dt 31-8-2024 | 621.395 ROT | 0006984 | 30.09.2024 | 695.00 | 30.09.2024 | INR | Books | |||||
| Dewey Decimal Classification | Non-fiction | IIITDM Kurnool | IIITDM Kurnool | ELECTRONICS COMMUNICATION ENGINEERING | 30.09.2024 | New India Book Agency | 695.00 | 5395 dt 31-8-2024 | 621.395 ROT | 0006985 | 30.09.2024 | 695.00 | 30.09.2024 | INR | Books | |||||
| Dewey Decimal Classification | Not For Loan | Reference | IIITDM Kurnool | IIITDM Kurnool | Reference | 30.09.2024 | New India Book Agency | 695.00 | 5395 dt 31-8-2024 | 621.395 ROT | 0006986 | 30.09.2024 | 695.00 | 30.09.2024 | INR | Reference |