000			01629nam a22001577a 4500
005			20240730100008.0
008			240730b |||||||| |||| 00| 0 eng d
020			_a9781489979278
082			_a621.381 _bNAV
100			_aNavabi, Zainalabedin
245			_aDigital System Test and Testable Design: _bUsing HDL Models and Architectures _cZainalabedin Navabi
260			_aUSA _bSpringer _c2011
300			_a435p
520			_aThis book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.
942			_2ddc _cBK
999			_c2346 _d2346