TY  - BOOK
AU  - Seligman,Erik
AU  - 
AU  - Schubert,E.Thomas
AU  - Kumar,M.V.Achutha Kiran
AU  - 
AU  - 
TI  - Formal verification: an essential toolkit for modern VLSI design 
SN  - 9780128007273
U1  - 621.3 SEL 23
PY  - 2015///]
CY  - Amsterdam, Boston
PB  - Elsevier/MK, Morgan Kaufmann is an imprint of Elsevier
KW  - Electronic circuits
KW  - Integrated circuits
KW  - Verilog (Computer hardware description language)
KW  - Testing
KW  - Very large scale integration
KW  - Design and construction
KW  - fast
N1  - Includes bibliographical references and index; Formal Verification: From Dreams to Reality;  Basic Formal Verification Algorithms;  Introduction to SystemVerilog Assertions;  Formal Property Verification;  Effective FPV For Design Exercise; Effective FPV for Verification; FPV "Apps" for Specific SOC Problems; Formal Equivalence Verification; Formal Verification's Greatest Bloopers: The Danger of False Positives; Dealing with Complexity Your New FV-Aware Lifestyle
N2  - 	
'Formal Verification' presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies
ER  -